stm32-usbd-devboards

STM32C0

The STM32C0 variant is based on the STM32C071K8T6 (ARM Cortex-M0+, 48 MHz) -- the newest addition to the lineup. Like the STM32F0 variant, it runs crystal-free using the HSIUSB48 internal oscillator self-calibrated via USB SOF packets, with an optional HSE crystal footprint on the board. The Cortex-M0+ core offers improved power efficiency over the Cortex-M0 in the F0, and this variant provides the largest pin count of the three boards with 2x14 headers exposing 28 GPIO + power pins.

Current Revision (20251110)

Resources:

• Schematic (PDF)
• Interactive BOM
• Gerber files

Supported Microcontrollers

The board uses the CMSIS device identifier STM32C071xx.

Pinout

Two 1x14 pin headers at 2.54 mm pitch -- the largest of the three variants.

Clocking

The default clock source is the HSIUSB48 internal oscillator at 48 MHz, self-calibrated via USB SOF packets from the host -- the same approach used by the F0 variant. No external crystal is needed for USB operation. For USB, firmware must enable the Clock Recovery System (CRS) peripheral synced from USB so that SOF packets continuously calibrate HSIUSB48. Without CRS enabled, the oscillator frequency will drift outside USB tolerance and communication will fail. CRS synced from USB is usually already enabled on reset.

An optional 48 MHz HSE crystal (Y1, HC49 package) can be installed if HSE is required for your application. When using HSE, it serves as the system clock directly -- STM32C0 devices have no PLL -- and HSIUSB48 is not needed. The solder bridges JP1/JP2 must remain open when HSE is installed, since PC14/PC15 serve as the oscillator pins.

The maximum system clock frequency is 48 MHz.

SWD and DFU Bootloader

The C0 variant uses a combined SWD + Bootloader header (J2) -- a single 5-pin vertical header that consolidates the separate SWD and bootloader headers found on the F0 and G4 variants.

Board-Specific Build Notes

• HSE crystal (Y1): Optional. 48 MHz, HC49 package. Only install if HSE is required.
• Solder bridges JP1/JP2: Open by default. Close only if the HSE crystal is not installed, to route PC14/PC15 to the header pins.
• LED (D1): Green 3 mm PTH, horizontal mount.

For the complete build process, see the generic Hardware Build Manual.

Firmware Development

For project setup, build system configuration, toolchain usage, and flashing instructions, refer to the cmake-cmsis-stm32 documentation. The CMSIS device identifier for this board is STM32C071xx.

For register-level details on clock configuration, CRS, USB peripheral, and GPIO, refer to the STM32C0 reference manual (RM0490).